The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the physical design methodology process of integrated systems. In modern electronic circuits, geometries become smaller; clock frequencies increase; and on-chip interconnections gain increased importance in the prediction of performance. Nonetheless, it has been found that from 0.13 μm and below, ICs are more susceptible to wear-out over time (electro-migration or EM) due to current densities, which requires some degree of built-in fault-tolerance and a careful design planning. Meanwhile, increased power demanded on ever shrunk chip size causes higher current densities within the power routing. Uni-directional current flow in analog designs also requires tracking of current densities in signal nets as well. Higher currents and/or higher operating temperatures induce more significant EM effects in which metal lines begin to wear out during a chip's lifetime. Such concerns have led to manufacturers creating current density limits for ICs and requiring designers to adhere to predefined current density limits.
The electro-migration problem in designing an electronic circuit is that there exist many unknowns until the very end of the design cycle in a conventional approach. Nevertheless, decisions about the structure, size and layout of many circuit component, e.g., the power grid, have to be made at very early stages when a large part of the chip design has not even begun. In addition, as VLSI technology scales, interconnects are becoming the dominant factor determining system performance and power dissipation. Interconnect reliability due to electro-migration is fast becoming a serious design issue particularly for long signal lines. In fact, it has been recently shown that interconnect Joule heating in advanced technology nodes can strongly impact the magnitude of the maximum temperature of the global lines despite negligible changes in chip power density which will, in turn, strongly affect the electro-migration lifetime of the interconnect. In analog designs, uni-directional current flow and smaller wire geometries create EM concerns for the signal nets as well.
Unfortunately, most conventional electronic circuit design tools focus on post-layout verification of interconnect when the entire chip design is complete and detailed information about the parasitics of the physical designs and the currents drawn by the transistors are known. Electro-migration problems revealed at this stage are usually very difficult or expensive to fix so the conventional methodologies help to design an initial electronic design and refine it iteratively at various design stages. In other words, the conventional circuit synthesis step is followed by layout synthesis and each step is carried out independent of the other. This is again followed by a physical or formal verification step to check whether the desired performance goals have been achieved after layout generation and extraction. These steps are carried out iteratively in such conventional approaches till the desired performance goals are met.
The behavior of analog circuits is even more sensitive to layout induced parasitics and thus electro-migration problems due to the unidirectional current flows in various circuit components. Parasitics not only influence the circuit performance but may often render it non-functional.
Thus, there exists a need for implementing electronic circuit designs with electro-migration awareness early in the design stage.